1. Field of the Invention
The present invention relates to a method for processing semiconductor products, and more particularly, to a method for manufacturing multi-kind and small-quantity semiconductor products in a mass-production line and a system thereof.
2. Description of the Related Art
Large quantities of semiconductor wafers in a lot are usually fabricated under the same processing conditions in a semiconductor manufacturing system. Such a mass-production method has greatly improved productivity of semiconductor products having the same specification in a large volume. However, if the mass-production method is applied to multi-kind and small-quantity semiconductor products, productivity of semiconductor products is lowered because processing conditions need to be frequently changed for the respective specifications of small-lot semiconductor products. Particularly, a recent increasing tendency in wafer diameter results in further decrease of a number of wafers in a lot fabricated under the same processing condition because a wafer of larger diameter has larger numbers of chips in a wafer, which further lowers productivity of semiconductor products. Therefore, it has been required to the semiconductor manufacturing system that the processing conditions can be changed quickly and flexibly for multi-kind and small-quantity semiconductor products, and that quality control can be carried out with respect to individual chips of various specifications without confusion.
Referring to FIG. 1, a conventional semiconductor manufacturing system used for manufacturing a semiconductor device is schematically illustrated. Main fabrication processing steps from 310 to 319 in the processing sequence are shown in the first row 301 while the corresponding apparatus, data and data transfer paths are also shown in the second, third and forth rows 302, 303, 304, respectively. When we look at the first column, layout patterns of circuits are designed in the first step 310, in which functions and characteristics of the final completed integrated circuit are determined, and then logic and circuit designs are carried out by using CAD, by which patterns and positions of circuit elements or interconnection layers therebetween are determined on a chip. The chip patterns include aligning marks and scribe lines therein needed for the wafer fabrication processing step.
Referring to FIG. 4, an example of the layout pattern of mask fabricated by the above conventional method is shown in relation to a wafer, in which a chip pattern 1, a mask-pattern 2 having repetitive pattern of the chip pattern and a wafer pattern 3 are also shown relatively. In the wafer fabrication processing step described later, transferring of the mask pattern 2 onto the wafer 3 needs to be carried out such that the largest number of chips can be obtained by the least number of shots in exposure. As shown in FIG. 4, a chip having a full area in both the mask-pattern and the wafer pattern is an effective chip for fabrication (shaded in the figure), while the non-shaded chips are ineffective chips located in each of four corners of the mask. Therefore, in designing of the layout pattern, the aligning of the mask pattern 2 to the wafer pattern 3 is optimized such that the largest number of the effective chips in a wafer is obtained. After the designing of the layout pattern is completed, the layout pattern is stored in a magnetic storage media such as magnetic cards, and then sent to the next mask processing step 311 by way of a data transferring path a′ as shown in FIG. 1. In a usual practical operation of the semiconductor manufacturing system, the foregoing magnetic storage media is manually set on an apparatus to be used for the next fabrication processing step by an operator. The rest of the data transferring paths from b′ to f′ shown in FIG. 1 are performed by the method similar to that of the data transferring path a′. In the mask fabrication processing step 311, the chip data in the layout data is transformed into photolithographic data readable by an electron beam exposure system. Then, a set of glass masks to be used for a plurality of the corresponding wafer processing steps are fabricated based on the transformed photolithographic data. In the wafer processing step 312, a plurality of the wafer processing steps are carried out by using the foregoing set of glass masks. Namely, after a conductive or insulating film is grown on the surface of a wafer by using a CVD system or a sputtering system, a photoresist film is coated thereon by spinner, and then the photoresist film is exposed by using a stepper with one from the set of glass masks. In the exposure step, an operator usually prints out the respective layout pattern shown in FIG. 4 on a paper or displays the same on a CRT to determine the relative position of the wafer to the glass mask. Next, etching patterns are formed by using an etching system with the delineated photoresist patterns on the wafer. A series of these wafer processing steps is repeated as many times as the number of the glass masks. The above described photolithographic processing step is generally applied to the pattern formation by full wafer aligning method. If higher accuracy of pattern formation is required, each of divided small regions on a wafer consisting of a chip or several chips is exposed repetitively step by step using a reticle, or alternately, a direct writing method by an electron beam exposure system. Next, in the wafer testing processing step 313 to which the wafers are transferred from the wafer fabrication processing step 312 ahead, after setting the initial conditions such as a starting position, moving direction and moving distance, chip characteristics of the wafers are measured. The measured result is recorded on a wafer map, in which the chip characteristics are recorded in relation with the corresponding chip address. The chip address is determined by choosing a base pattern formed in advance on the wafer as a mark for the standard position. Furthermore, in the wafer testing step 313, after defect chips are marked with a fault mark on the wafer based on the wafer map formed ahead, the wafer is transferred to the wafer breaking processing step. In the wafer breaking processing step 314, after the base pattern on the wafer is detected by detector, the wafer map accompanied with the wafer is read. Then, by aligning the wafer to the wafer map using the base pattern already detected, the initial conditions such as a starting position, moving direction and moving distance can be set for a dicing machine. Chips are separated from the wafer and then only good chips are selectively separated from the defect chips with the fault mark, and then, transferred to the next assembly step. Similarly, in the assembly step 315, after a starting position, moving direction and moving distance are set based on the wafer map for the wire bonding apparatus, each of the good chips fed from the wafer breaking processing step is mounted on a package. After the visual inspection is carried out with the packages, the packages excluding defect packages therefrom are transferred to the IC testing step. In the IC testing step 316, again on the base of the wafer map transferred hereto together with the IC packages, after setting the initial conditions for the tester, the semiconductor IC in a package is tested to screening good IC's from defect ones. Additionally, the screened semiconductor IC may be, upon request, divided into groups with respect the testing result and then transferred to the shipping step 319.
As explained above, the semiconductor manufacturing system is operated such that a plurality of fabrication processing steps are carried out sequentially but separately from one another to complete a semiconductor integrated circuit device. That is to say, the wafer transferred from the neighboring step ahead is processed in the present step, and then transferred to the next step successively. In each of the steps, a common test such as a visual inspection is performed on every chips of the processed wafer to screen defective chips, and then the testing result is recorded in the wafer map and sent to the next step in which the next processing step is executed referring the wafer map. On the wafer map, the testing result on each of chips on the wafer is recorded together with the respective address, which is indicated by chip coordinates. Additionally, lot numbers identifying manufacturing date and specifications, wafer numbers identifying wafers in a lot and chip numbers identifying chips on a wafer are also recorded on the same wafer map. The lot numbers, wafer numbers, chip numbers and coordinates are used as chip identification information formed on a wafer. The chip identification information is coded into an identification code formed on the wafer by the common fabrication processing steps with those of layout patterns. The chip identification code enables an operator to identify an individual chip on a wafer as well as to confirm the chip characteristics by referring the corresponding chip identification information recorded on the wafer map. Since, in the wafer breaking step or assembly step, a large number of chips are separated from one wafer to be processed individually, it is needed that the identification code can avoid from confusing the separated chips, and manages quality control of individual completed products. Since, in the layout pattern designing step 310, more or less, manufacturing system and date, or wafer dimension and batch size are still undetermined, it is difficult to determine the chip identification information at this stage. Consequently, lithography data for a mask or reticle, or an electron beam lithography system to form a chip identification code on a wafer is generated separately from data for circuit layout patterns, and then sent to the manufacturing system together with the data for circuit layout patterns at the beginning of the wafer fabrication processing steps. As an alternative method for identifying individual chips on a wafer to the foregoing method, it is proposed that individual chips have their memory circuits thereon to write and read the chip identification information. However, a drawback is that the memory circuits for this specific purpose occupies an extra silicon real estate.
In the semiconductor manufacturing system, in addition to the foregoing processing steps, data superposing analysis is performed to investigate the reasons for decreasing yield of products, in which, as shown in FIG. 1, data is sent to the data superposing analysis member 317 from respective processing steps. Since data generated by each of the processing systems is generally different in data format from each other, the data must be transformed into the common data format by data transformation system 318 before the data sent to the data superposing analysis member 317. In general, chip size or dimension and location of I/O terminals in a chip are different from each other between IC products, and that some steppers, probers or fabrication processing systems are also different in operating method or protocol from each other. Resultantly, when the semiconductor manufacturing system is operated, the initial setting conditions must be given to each of the various fabrication processing steps or testing systems for every respective products having different specifications. Particularly to a diversified and small quantity production, it is nuisance to change various setting conditions as frequently as the numbers of the respective batches of a small quantity wafers.
In the conventional semiconductor manufacturing system, whenever wafers and the wafer maps are transferred from the step ahead, identifying whether or not the setting conditions must be changed, and then the necessary changes are made. For instance, in wafer fabrication processing steps, after reading the lot number on a wafer, the initial setting conditions must be given to each of the various fabrication processing systems, and in wafer testing step, after reading chip coordinates and lot number on a wafer, chip dimension, numbers of pads for I/O terminals on the chip and difference in their allocations must be confirmed and then the setting conditions must be given in the initial allocations, amount and direction of motion. Since a normal wafer processing operation begins after all the preparing operations as described above are completed, it takes much time to begin the normal processing operation on the wafer coming in from the preceding step for every respective products having different specifications.
Consequently, when the conventional semiconductor manufacturing system is applied to a diversified and small quantity production, there are drawbacks such that not only a percentage of time required for the preparing operations for every respective products before the normal processing operation on the wafer begins increases but also errors in the operation easily increase, which result in lowering of productivity. Additionally, there is the following problem in forming the identification code on a wafer. The layout pattern is usually composed of repetition of a single pattern on a wafer. In contrast, the identification code differs in its pattern from chip to chip on a single wafer. Therefore, if the conventional lithographic method is applied to a small area for the identification code pattern using reticles, a large number of the reticles specifically prepared are needed for each of step-and-repeat exposures, which incurs more complexity in processing steps and higher cost. On the other hand, all of the identification codes can be formed on the respective chips on a wafer by full-wafer exposure photolithography with a single mask, which may be simpler and less expensive. However, since the full-wafer exposure photolithography has been already incompatible with recent fine patterning techniques such as the step-and-repeat exposure method using reticles or the electron beam direct writing method, adopting the full-wafer exposure photolithography is impractical for a single purpose to form patterns of the identification codes. In particular, the method that a specific memory circuit is formed on the same chip results in increase of an extra chip area for the specific memory circuit and steps for reading and writing data, both of which make cost higher. The electron beam direct writing method for forming identification code on each of chips on a wafer has an advantage in compatibility with layout pattern formation as well as the step-and-repeat exposure method using reticles. However, it is necessary for the layout pattern formation by electron beam direct writing method that, to maintain pattern accuracy by limiting a deflection angle of the electron beam below a certain value, similarly to the step-and-repeat exposure method using reticles, an individual writing operation on every small areas on a wafer is repeated step by step. In other words, writing data fed to the electron beam direct writing system is edited in a unit for each of the small areas, by which after setting an initial position of an electron beam irradiation, each of the small areas is continuously irradiated by the electron beam to write layout patterns. A series of the writing operations are repeated for all of the small areas by setting an initial position of an electron beam irradiation. Applying this method to pattern formation of the identification codes to make compatibility with the layout pattern formation, in spite of the fact that pattern formation of the identification codes does not require such high accuracy as formation of the layout pattern, the same high accuracy is applied to the pattern formation of the identification code, which results in unnecessarily long time for the electron beam writing operation. Furthermore, since pattern formation of the identification codes is carried out in the early stage of the electron beam writing operation on a wafer, information on a testing result occurred in the later processing step, for instance, information obtained in the chip testing step, can not be contained in the identification codes, and that the information can not be obtained unless the wafer map is referred. Consequently, it incurs much time and labor, and even inadvertent mistakes to know the testing result of a specific chip, particularly after separating chips from a wafer.